Jin Yang - Postsilicon Verification
Abstract: The quality of a System-On-Chip (SoC) product is ensured through three distinct but serialized processes: pre-silicon validation of the design, post-silicon validation of the development chips, and testing of each production chip during high volume manufacturing. While pre-silicon validation and testing have benefited tremendously from years of active research, post-silicon validation is still largely an immensely intensive and complicated engineering practice that today has become a dominating factor in the cost and time of developing an SoC product. The challenges of post-silicon validation come from high complexity and integration on-die, sophisticated performance/power management, increasing amount of embedded software, and at the same time very limited observability and controllability. As a result, post-silicon validation is an emerging area with unique opportunities for major innovations in applying formal methods to solve real world problems.
In this talk, we first examine the current practice of post-silicon validation and how it relates to but differs from traditional pre-silicon verification. We focus on several areas critical for reducing the cost and time of post-silicon validation that can potentially benefit from formal methods research. Among these areas are validation coverage definition and content optimization, triage and debug automation, and design and validate on-die validation systems. We then survey several recent advances leveraging formal methods that have made impact or have potential impact to post-silicon vacation. Finally, we provide an overview of our research work on a symbolic analysis technique for isolating silicon speed-paths.