FMCAD 2010
Call for Papers
International Conference on Formal Methods in Computer-Aided Design
Lugano, Switzerland
20-23 October 2010
http://fmcad10.iaik.tugraz.at/
Call for Papers in PDF
IMPORTANT DATES
Abstract Submission: 5 May 2010
Paper Submission: 12 May 2010 (23:59 Samoa time, UTC-11)
Author Notification: 7 July 2010
Final Version: 28 July 2010
Conference: 20-23 October 2010
CONFERENCE SCOPE
FMCAD 2010 is the tenth in a series of conferences on the theory and
application of formal methods in hardware and system design and
verification. FMCAD provides a leading international forum to
researchers and practitioners in academia and industry for presenting
and discussing novel methods, technologies, theoretical results, and
tools for formally reasoning about computing systems, as well as open
challenges therein. This year, FMCAD is privileged to have Joseph
Sifakis, Founder and Director of VERIMAG Laboratory, a Turing Award
2007 winner, to deliver its keynote address on Scientific Challenges
and Work Directions in Embedded Systems Design. The tutorial speakers
are Ken McMillan, a Paris Kanellakis Award winner, senior researcher
at Cadence Berkeley Labs, Warren Hunt, Professor at University of
Texas at Austin, Sumit Gulwani, a researcher at Microsoft Research,
USA, and Jin Yang, a senior staff research engineer at Intel
Strategic CAD Labs.
NEW: FMCAD 2010 has two tracks (but no parallel sessions): the
research track and the industrial track.
RESEARCH TRACK
Topics of interest:
Advancing industrial-strength technologies in Model Checking,
Theorem Proving, Equivalence Checking, Abstraction and Refinement
Techniques, Reduction and Abstraction Techniques, Compositional
Methods, Decision Procedures, SMT solvers, Bit-Precise Reasoning,
Word-Level Techniques, SAT- and BDD-based methods, Probabilistic
Methods, and Combinations of Deductive Methods and Decision
Procedures.
Applications of Formal Methods in Specification, Design and
Verification
Topics relating to the application and applicability of Property-Based
Verification, Equivalence Checking, Semi-formal Verification, Runtime
Verification, Simulation and Test-case Generation, Coverage Analysis,
Microcode Verification, Concurrent Systems, Timing Verification, and
Formal Approaches to Performance and Power.
System-Level Design and Verification, especially for Embedded
Systems, Software Verification, HW/SW Co-Design and Verification,
Transaction-Level Verification.
Modeling and Specification Languages, Model-Based Design,
Verification-Based Testing, Design Derivation and Transformation,
Correct-by-Construction Methods.
INDUSTRIAL TRACK
This track is dedicated to industry users of formal methods, including
work on real industrial-scale designs being done in universities and
research organizations. We invite such users to describe their experience with
formal methods, including evaluations of commercial tools, case studies of
industrial-scale applications, experience reports on novel and challenging
applications, or methodologies for the incorporation of formal or semi-
formal methods into the industrial design flow. Finally, we invite tool
presentations, of industrial-strength commercial tools as well as novel
academic tools that are not yet industrial strength, but address a real
industrial need. Tool presentations should describe the capabilities or
novel features of the tool, or an innovative algorithm, a new approach,
or original application methodology.
EXHIBITION
FMCAD 2010 will feature also an exhibition with limited free-of-charge
booth space for which academic novelty is not a requirement. Note that
since space is limited, we will not be able to accept every request for a booth,
and that preference will be given to requests by authors of accepted tool
presentations. EDA vendors are especially encouraged to submit a tool
presentation and/or to request booth space in order to demo their tools.
SUBMISSIONS
Submissions must be made electronically in PDF format via EasyChair.
More details will be provided on the FMCAD web site. The
proceedings are planned to be published by IEEE and ACM and will be
available online in the ACM Digital Library and at IEEE Xplore.
Research Track Submissions
Two categories of research papers can be submitted: regular papers (8
pages) containing original research, and short papers (4 pages) describing
emerging results and work-in-progress.
Industrial Track Submissions
Submitters to the industrial track will have the option of submitting a
regular paper (8 pages), a short paper (4 pages), or a deck of up to
25 slides (for tool presentations: 4 pages or 15 slides). Both papers
and slide submissions will be reviewed. Regular and short papers will
appear in the proceedings as usual, while authors of accepted slide
presentations will be invited to write a one page abstract for the
proceedings.
For exhibition space, submission is not required and an email request to
the industrial track chairs is sufficient. However, due to limited space
we will not be able to accept every request. We therefore strongly
advise those interested in exhibition space to submit a tool presentation,
as we will give preference for booth space to authors of accepted tool
presentations.
Regular and short papers must use the IEEE Transactions format on
letter-size paper using a 10-point font. (See
http://www.ieee.org/conferences_events/conferences/publishing/templates.html.)
Research Track papers must contain original research that has not been
previously published, nor concurrently submitted for publication. For
both research and industry submissions, any partial overlap with a
published or concurrently submitted paper must be clearly indicated.
(For slide decks, use an extra slide to discuss overlaps; this slide may
be excluded from the final presentation.) By submitting their work,
the authors agree to present it at the conference if selected. Authors
are strongly encouraged to provide adequate access to their
experimental data for verification.
A small number of accepted papers will be considered for a
distinguished paper award.
CHAIRS
Roderick Bloem, Graz University of Technology, Austria
Natasha Sharygina, University of Lugano, Switzerland and Carnegie Mellon University, USA
INDUSTRIAL TRACK CHAIRS
Wolfgang Ecker, Infineon, Germany
Cindy Eisner, IBM Haifa Research Laboratory, Israel
TUTORIAL CHAIR
Helmut Veith, Vienna University of Technology, Austria
PUBLICATION CHAIR
Hana Chockler, IBM Haifa Research Laboratory, Israel
PROGRAM COMMITTEES
Technical Program:
Jason Baumgartner, IBM, USA
Valeria Bertacco, University of Michigan, USA
Armin Biere, Johannes Kepler University, Austria
Per Bjesse, Synopsys, Inc., USA
Roderick Bloem, Graz University of Technology, Austria
Doron Bustan, Intel, Israel
Gianpiero Cabodi, Politecnico di Torino, Italy
Alessandro Cimatti, IRST, Italy
Koen Claessen, Chalmers University of Technology, Sweden
Ganesh Gopalakrishnan, University of Utah, USA
Aarti Gupta, NEC Labs, USA
Ziyad Hanna, Jasper Design Automation, USA
Alan Hu, University of British Columbia, Canada
Barbara Jobstmann, CNRS-Verimag, France
Jie-Hong Roland Jiang, National Taiwan University, Taiwan
Vineet Kahlon, NEC, USA
Gerwin Klein, NICTA, Australia
Daniel Kroening, Oxford University Computing Laboratory, UK
Thomas Kropf, University of Tübingen, Germany
Marta Kwiatkowska, Oxford University Computing Laboratory, UK
Oded Maler, CNRS-Verimag, France
Panagiotis Manolios, Northeastern University, USA
Ken McMillan, Cadence Berkeley Labs, USA
Tom Melham, Oxford University Computing Laboratory, UK
John O'Leary, Intel, USA
Lee Pike, Galois, Inc., USA
Marc Pouzet, University of Paris-Sud, France
Julien Schmaltz, Open University of The Netherlands, Netherlands
Natarajan Shankar, Computer Science Laboratory, SRI, USA
Natasha Sharygina, University of Lugano, Switzerland and Carnegie Mellon University, USA
Satnam Singh, Microsoft Research
Anna Slobodova, Centaur, USA
Sofiene Tahar, Concordia University, Canada
Helmut Veith, Vienna University of Technology, Austria
Karen Yorav, IBM Research, Israel
Industrial track:
Peter Jensen, SyoSil Aps, Denmark
Pranav Ashar, RealIntent, USA
Lyes Benalycherif, ST Ericsson, France
Per Bjesse, Synopsys, Inc., USA
Holger Busch, Infineon
Joachim Gerlach, Albstadt-Sigmaringen University, Germany
Ziyad Hanna, Jasper Design Automation, USA
Christian Jacobi, IBM, Germany
Andreas Kuehlmann, Cadence Berkeley Labs, USA
Ajeetha Kumari, CVC Pvt Ltd, India
Viresh Paruthi, IBM, USA
Axel Scherer, Cadence Design Systems. Inc, USA
Michael Siegel, OneSpin Solutions, Germany
LOCAL ARRANGEMENTS
Mariagiovanna Sami, Politecnico di Milano, Italy and University of Lugano, Switzerland
Umberto Bondi, University of Lugano, Switzerland
Daniela Dimitrova, University of Lugano, Switzerland
Francesco Regazzoni, University of Lugano, Switzerland and UCL Louvain-la-Neuve, Belgium
STEERING COMMITEE
Jason Baumgartner, IBM, USA
Aarti Gupta, NEC Labs, USA
Warren Hunt, University of Texas at Austin, USA
Panagiotis Manolios, Northeastern University, USA
Mary Sheeran, Chalmers University of Technology, Sweden